New in 2019: Systems papers submitted to Track 1 do not necessarily need to consider timing issues to be in scope.
RTAS is a top-tier conference with a focus on systems research related to embedded systems or timing issues. The broad scope of RTAS’19 ranges from traditional hard real-time systems to embedded systems without explicit timing requirements, including latency-sensitive systems with informal or soft real-time requirements.
RTAS’19 invites papers describing original systems and applications, case studies, methodologies, and applied algorithms that contribute to the state of practice in the design, implementation, verification, and validation of embedded systems and time-sensitive systems (of any size). The scope of RTAS’19 consists of three tracks:
- Applications, Operating Systems, and Run-Time Software,
- Applied Methodologies and Foundations, and
- Hardware Architectures and Analysis Tools.
Timing requirements of interest include not only classical hard real-time constraints, but also time-sensitive applications in a broader sense, including applications subject to probabilistic, soft real-time, quality-of-service (QoS), or latency requirements. For example, relevant application areas include (but are not limited to):
- time-sensitive cloud/edge/fog computing systems (e.g., characterized by a focus on tail latency);
- time-sensitive applications in the Internet of Things (IoT);
- time-sensitive distributed event processing systems;
- time-sensitive mobile computing apps;
- timing aspects in robotics middlewares and frameworks;
- machine learning in time-sensitive systems;
- real-time control in smart cities and other large cyber-physical systems (CPS);
- signal processing algorithms that must execute in real time; and
- real-time healthcare solutions.
RTAS’19 welcomes both papers backed by formal proofs as well as papers that focus exclusively on empirical validation of timing requirements. Track 1 further welcomes applied systems papers that focus on practical issues other than timing in the broader field of embedded/CPS/IoT systems and applications.
The conference proceedings will be published by IEEE and indexed on IEEE Explore. RTAS’19 follows a double-blind peer reviewing process: author identities and affiliations will not be revealed to reviewers.
Track 1: Applications, Operating Systems, and Run-Time Software
The systems track focuses on research of an empirical nature pertaining to applications and runtime software for time-sensitive and/or embedded systems. Applied systems papers that target embedded systems do not necessarily need to consider timing issues. Relevant areas include, but are not limited to, real-time and embedded operating systems, CPS and IoT infrastructure, platforms for time-sensitive cloud computing and data processing, middleware, tools, and case studies. Papers discussing design and implementation experiences on real industrial systems are especially encouraged. Papers submitted to this track should focus on specific systems and implementations. Authors must include a section with experimental results performed on a real implementation, or demonstrate applicability to an industrial case study or working system. The experiment or case study discussions must highlight the key lessons learned. Simulation-based results are acceptable in exceptional cases only if the authors clearly motivate why it is not possible to develop and evaluate a real system.
Track 2: Applied Methodologies and Foundations
This track focuses on fundamental models, techniques, methods, and analyses that are applicable to time-sensitive systems to solve specific problems. For submissions to be in scope for Track 2, the work must consider some form of timing requirements, which includes both classical hard or soft real-time systems as well as latency-sensitive systems in domains such as (but not limited to) CPS, IoT, or the Cloud. General topics relevant to this track include, but are not limited to: scheduling and resource allocation, specification languages and tools, system-level optimization and co-design techniques, design space exploration, verification and validation methodologies. Papers must describe the main context or use-case for the proposed methods giving clear motivating examples based on real systems. The system models and any assumptions used in the derivation of the methods must be applicable to real systems and reflect actual needs. Papers must include a section on experimental results, preferably including a case study based on information from a real system. The use of synthetic workloads and models is however acceptable if appropriately motivated and used to provide a systematic evaluation.
Track 3: Hardware Architectures and Analysis Tools
This track focuses on novel hardware/software architectures and analysis techniques that relate to the behavior of real hardware in the context of time-sensitive systems. Topics relevant to this track include, but are not limited to: worst-case execution time analysis, analyses of cache, memory hierarchies and communication infrastructures, SoC design for real-time applications, special purpose functional units and GPUs, specialized memory structures, chip multiprocessors and interconnects, FPGA simulation and prototyping, simulation, compilation and synthesis of novel architectures and applications, and power- and energy-aware analyses and architectures. Papers must include a section on experimental results, preferably including a case study based on information from a real system, and motivate how the presented work pertains to time-sensitive systems. The use of synthetic workloads and models is however acceptable if appropriately motivated and used to provide a systematic evaluation.